1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of designing the same, and more particularly, it relates to a semiconductor integrated circuit device including a circuit block having a hierarchical structure and a method of designing the same.
2. Description of the Prior Art
In recent years, a semiconductor integrated circuit device applied to an electronic device or the like must be miniaturized, weight-saved, power-saved and reduced in cost. In consideration of such requirements, a system LSI prepared by providing a memory and various types of logic circuits on a single chip is developed. A method of designing a semiconductor integrated circuit device with reference to a basic unit of a circuit block, also referred to as a functional block (IP), including a number of cells implementing certain functions is generally known as a design technique corresponding to such a system LSI. In relation to such a method of designing a semiconductor integrated circuit device with reference to the basic unit of the circuit block, a method of designing a semiconductor integrated circuit device by creating a hierarchical structure with reference to the basic unit of the circuit block is also known.
In the aforementioned method of designing a semiconductor integrated circuit device by creating the hierarchical structure with reference to the basic unit of the circuit block, a method using a gated clock employing a gate turning on a clock only when necessary is also proposed as a method of reducing power consumption. This gated clock is described in xe2x80x9cTechnical White Paper of Low-Power LSIsxe2x80x9d, extra issue of Nikkei Microdevices by Nikkei Business Publications, Inc., 1994, p. 80, for example.
Further, Japanese Patent Laying-Open No. 2000-123059, for example, discloses a method of designing a semiconductor integrated circuit device with reference to a basic unit of the aforementioned circuit block. This gazette discloses a design method reducing power consumption by sharing parts sharable between blocks in a single hierarchy.
However, the aforementioned gazette discloses only a design method related to reduction of power consumption in a single hierarchy, with no disclosure of a design method related to reduction of power consumption in a hierarchical structure. In general, therefore, it is difficult to provide a simple design method for reducing power consumption in relation to design of a semiconductor integrated circuit device including a plurality of circuit blocks having a hierarchical structure. Particularly when the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies, the hierarchical structure is so complicated that it is difficult to provide a simple design method related to reduction of power consumption. In general, therefore, it is difficult to design a semiconductor integrated circuit device of low power consumption by a simple method if the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies.
When the semiconductor integrated circuit device has a hierarchical structure, the structure of a gated clock employed for reducing power consumption is generally disadvantageously complicated. Particularly when the semiconductor integrated circuit device has a hierarchical structure including at least three hierarchies, the hierarchical structure is complicated to result in remarkable complicatedness of the structure of the gated clock. In order to change the design of the semiconductor integrated circuit device for changing the combination of the circuit blocks or the hierarchical structure, further, the structure of the gated clock must be newly redesigned in general. In general, therefore, it is difficult to simply design the structure of the gated clock for changing the design of the semiconductor integrated circuit device.
An object of the present invention is to readily obtain a semiconductor integrated circuit device of low power consumption by selecting a gated clock for reducing power consumption by a simple method when the semiconductor integrated circuit device has a hierarchical structure.
Another object of the present invention is to provide a method of designing a semiconductor integrated circuit device capable of readily selecting a gated clock for reducing power consumption when the semiconductor integrated circuit device has a hierarchical structure.
A semiconductor integrated circuit device according to a first aspect of the present invention comprises a plurality of circuit blocks having a hierarchical structure including at least three hierarchies and outputting an operation control signal from each upper hierarchy to each lower hierarchy, and employs at least one gated clock selected from a group including at least three gated clocks consisting of at least two gated clocks generated by employing at least two operation control signals output to different hierarchies as gate signals and a prescribed gated clock input in a circuit block of the most significant hierarchy as a gated clock input in a circuit block of a lower hierarchy below a third hierarchy among the plurality of circuit blocks. The semiconductor integrated circuit device of the present invention includes a semiconductor integrated circuit device in the designing stage.
According to the aforementioned structure, the semiconductor integrated circuit device according to the first aspect mechanically simply decides a plurality of gated clocks for reducing power consumption on the basis of the operation control signal and the prescribed gated clock input in the circuit block of the most significant hierarchy. When at least one gated clock satisfying a prescribed circuit constraint is selected from the plurality of gated clocks, a semiconductor integrated circuit device of low power consumption can be readily obtained.
In the semiconductor integrated circuit device according to the aforementioned first aspect, a master clock is preferably input in a circuit block of a first hierarchy defining the most significant hierarchy among the plurality of circuit blocks as the gated clock, and a circuit block of a second hierarchy defining a lower hierarchy for the first hierarchy preferably receives either a gated clock generated by employing an operation control signal output from the circuit block of the first hierarchy to the second hierarchy as a gate signal or the master clock. According to this structure, the gated clocks input in the circuit blocks of the first and second hierarchies for reducing power consumption can be readily selected.
In the semiconductor integrated circuit device according to the aforementioned first aspect, at least one gated clock satisfying a prescribed circuit constraint among the plurality of gated clocks included in the aforementioned group is preferably input in the circuit block below the third hierarchy. According to this structure, at least one gated clock satisfying the prescribed circuit constraint is input in the circuit block below the third hierarchy, whereby optimized gated clocks satisfying the prescribed circuit constraint can be readily supplied in the circuit blocks having the hierarchical structure. In this case, the prescribed circuit constraint preferably includes such a constraint that a single gated clock operates at least a prescribed number of flip-flops. According to this structure, it is possible to select a gated clock more suitable for low power consumption than a case of flip-flops operating in excess of the prescribed number. Thus, a semiconductor integrated circuit device capable of further reducing power consumption can be obtained.
In the semiconductor integrated circuit device according to the aforementioned aspect, the circuit block of the lower hierarchy preferably operates only during operation of the circuit block of the upper hierarchy.
In the semiconductor integrated circuit device according to the aforementioned first aspect, each circuit block preferably includes a data holding circuit for holding data and a selection circuit for selecting whether or not to hold newly input data in the data holding circuit on the basis of the operation control signal. According to this structure, whether or not to hold the data can be readily selected on the basis of the operation control signal. In this case, the data holding circuit preferably includes a flip-flop, and the selection circuit includes a selector for selecting whether or not to latch new data in the flip-flop. In this case, the flip-flop preferably latches and holds an input signal in response to the selector only when the operation control signal is ON, and the flip-flop preferably outputs held data when the operation control signal is OFF. According to this structure, whether or not to hold the input signal in the flip-flop can be readily selected.
The semiconductor integrated circuit device according to the aforementioned first aspect preferably further comprises a gated clock generation part for generating the gated clock, and the gated clock generation part preferably includes a flip-flop and an AND circuit. According to this structure, the gated clock can be readily generated.
In the semiconductor integrated circuit device according to the aforementioned first aspect, each circuit block may be supplied with a single gated clock.
A method of designing a semiconductor integrated circuit device according to a second aspect of the present invention is a method of designing a semiconductor integrated circuit device comprising a plurality of circuit blocks having a hierarchical structure including at least three hierarchies and outputting an operation control signal from each upper hierarchy to each lower hierarchy, comprising steps of selecting at least one gated clock from a group including at least three gated clocks consisting of at least two gated clocks generated by employing at least two operation control signals output to different hierarchies as gate signals and a prescribed gated clock input in a circuit block of the most significant hierarchy as a gated clock input in a circuit block of a lower hierarchy below a third hierarchy among the plurality of circuit blocks and designing for inputting at least one selected gated clock in the circuit block below the third hierarchy.
The method of designing a semiconductor integrated circuit device according to the second aspect mechanically simply decides a plurality of gated clocks for reducing power consumption on the basis of the operation control signal and the prescribed gated clock input in the most significant hierarchy according to the aforementioned structure. When at least one gated clock satisfying a prescribed circuit constraint is selected from the plurality of gated clocks, therefore, a semiconductor integrated circuit device of low power consumption can be readily designed. Also when the design is changed for changing the combination of the circuit blocks or the hierarchical structure, the gated clocks input in the circuit blocks can be readily selected on the basis of the operation control signals and the gated clock input in the most significant hierarchy. Therefore, the design of the circuit blocks can also be readily changed.
In the method of designing a semiconductor integrated circuit device according to the aforementioned second aspect, the step of selecting at least one gated clock input in the circuit block of the lower hierarchy below the third hierarchy preferably includes a step of selecting at least one gated clock satisfying a prescribed circuit constraint from the plurality of gated clocks included in the group. In this case, the step of selecting at least one gated clock satisfying the prescribed circuit constraint preferably includes steps of determining whether or not a first gated clock generated through the operation control signal for the lower hierarchy satisfies the prescribed circuit constraint and selecting the first gated clock when the first gated clock satisfies the prescribed circuit constraint while replacing the first gated clock with a second gated clock for the upper hierarchy satisfying the prescribed circuit constraint when the first gated clock does not satisfy the prescribed circuit constraint. According to this structure, the gated clock satisfying the prescribed circuit constraint can be automatically selected. In this case, the prescribed circuit constraint includes such a constraint that a single gated clock operates at least a prescribed number of flip-flops. According to this structure, it is possible to select a gated clock more suitable for low power consumption than a case of flip-flops operating in excess of the prescribed number. Thus, a semiconductor integrated circuit device capable of further reducing power consumption can be designed. In the aforementioned case, the method of designing a semiconductor integrated circuit device preferably further comprises a step of deleting the unnecessary first gated clock for the lower hierarchy when replacing the first gated clock with the second gated clock for the upper hierarchy. According to this structure, the gated clock satisfying the circuit constraint can be automatically selected.
In the method of designing a semiconductor integrated circuit device according to the aforementioned second aspect, a master clock is preferably input as the gated clock in a circuit block of a first hierarchy defining the most significant hierarchy among the plurality of circuit blocks, and a circuit block of a second hierarchy defining a lower hierarchy for the first hierarchy preferably receives either a gated clock generated by employing an operation control signal output from the circuit block of the first hierarchy to the second hierarchy as a gate signal or the master clock. According to this structure, gated clocks input in the first and second hierarchies for reducing power consumption can be readily selected.
The method of designing a semiconductor integrated circuit device according to the aforementioned second aspect preferably operates the circuit block of the lower hierarchy only during operation of the circuit block of the upper hierarchy.
In the method of designing a semiconductor integrated circuit device according to the aforementioned second aspect, each circuit block preferably includes a data holding circuit for holding data and a selection circuit for selecting whether or not to hold newly input data in the data holding circuit on the basis of the operation control signal, the data holding circuit preferably holds an input signal in response to the selection circuit only when the operation control signal is ON, and the data holding circuit outputs held data when the operation control signal is OFF. According to this structure, whether or not to hold the input signal in the data holding circuit can be readily selected on the basis of the operation control signal. In this case, the data holding circuit preferably includes a flip-flop, and the selection circuit preferably includes a selector for selecting whether or not to latch new data in the flip-flop.
The method of designing a semiconductor integrated circuit device according to the aforementioned second aspect preferably further comprises a step of providing a gated clock generation part, having a flip-flop and an AND circuit, for generating the gated clock. According to this structure, a semiconductor integrated circuit device capable of generating a gated clock can be readily designed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.